1. Field of the Invention
The present invention relates to a video signal processing circuit, more particularly relates to a data slice circuit for separating a variety of data superposed on an input video signal.
2. Description of the Related Art
A data slice circuit separates, digitizes, and outputs data added to (placed on) a prescribed signal superposed on a television (TV), digital television, or other video signal at the vertical blanking interval (VBI) (VBI signal), for example, a closed caption (EIA-608), ID-1 (EIAJ-CPR1204), European teletext (teletext)/VPS, or other VBI signal.
VBI signals superposed on a television, digital television, or other video signal at the vertical blanking interval can be roughly divided into ones having (including) a clock-run-in (CRI) signal such as a closed caption and teletext signal and ones only having a reference signal without having (including) a CRI signal such as an ID-1 signal.
As a data slice circuit of the related art for separating data of a VBI signal having a CRI signal, there is known for example the circuit disclosed in Japanese Unexamined Patent Publication (Kokai) No. 10-336609.
Also, as a data slice circuit of the related art for separating data of a VBI signal only having a reference signal, for example, there is known the circuit described in Japanese Unexamined Patent Publication (Kokai) No. 6-253170.
FIG. 8 is a circuit diagram of the data slice circuit of the related art for separating data of a VBI signal having a CRI signal described in Japanese Unexamined Patent Publication (Kokai) No. 10-336609.
The data slice circuit 10 comprises, as shown in FIG. 8, a top peak detector 11, a bottom peak detector 12, a sampling/holding circuit 13, a composite synchronous signal separation circuit 14, a CRI window circuit 15, a comparator 16, and resistors R11 and R12.
In the data slice circuit 10, a top peak of an input video signal, that is, VBI signal, is detected by the top peak detector 11, while a bottom peak is detected by the bottom peak detector 12.
Outputs of the top peak detector 11 and the bottom peak detector 12 which detected the top peak and the bottom peak of the input VBI signal are spliced at the resistors R11 and R12. Since the resistors R11 and R12 are set to have the same resistance values, an intermediate voltage value of the top level and the bottom level is supplied from a node P to the sampling/holding circuit 13.
Also, the CRI window circuit 14 is supplied with a composite synchronous signal CSS separated by the composite synchronous signal separation circuit 14. In the CIR window circuit 14, a control signal S15 for controlling sampling and holding operations based on the composite synchronous signal CSS is generated and output to the sampling/holding circuit 13.
In the sampling/holding circuit 13, the voltage is sampled and held in a CRI signal interval and it is output as a reference voltage (slice level) to the comparator 16 in accordance with a control signal S15 from the CRI window circuit 14.
The comparator 16 separates the data by comparing the input VBI signal with the slice level.
FIG. 9 is a circuit diagram of the data slice circuit of the related art for separating data of an VBI signal only having a reference signal described in Japanese Unexamined Patent Publication (Kokai) No. 6-253170.
The data slice circuit 20 comprises, as shown in FIG. 9, a synchronous signal clamping circuit 21, a reference voltage source 22, buffers 23 and 24, a sampling/holding (S/H) circuit 25, an operational amplifier 26, comparators 27 and 28, a clamp capacitor C21, and resistors R21 to R24.
In the data slice circuit 20, an input VBI signal is input to the synchronous signal clamping circuit 21 via the clamp capacitor C21. In the synchronous signal clamping circuit 21, a synchronous signal included in the VBI signal is clamped to a clamp level Vc supplied by the reference voltage source 22, the clamped VBI signal is supplied as a signal to be sliced to the comparators 27 and 28, and it is supplied to the sampling/holding circuit 25 via the buffer 23.
In the sampling/holding circuit 25, the clamped VBI signal is sampled and held by a pedestal level, the pedestal level Vp is detected, and the same is supplied to the operational amplifier 26 via the buffer 24 for computing the slice level in the comparators 27 and 28.
Also, the potential difference of the detected pedestal level Vp and the clamp level Vc is spliced at the resistors R21 and R22. The splice level Vs1 is supplied to the comparator 27. As a result, in the comparator 27, the processing for separating a synchronous signal is performed.
In the operational amplifier 26, the detected pedestal level Vp is input to a non-inverted input terminal (+) and the clamp level Vc is supplied to an inverted input terminal (−) via the resistor R23. Then, in the operational amplifier 26, a slice level Vs2 is generated based on the pedestal level Vp, clamping level Vc, a resistance value of the resistor R222, and a resistance value of a feedback resistor R24 as a slice level of the comparator 28 and this is output to the comparator 28. As a result, in the comparator 28, the processing for slicing data superposed on the input VBI signal at the vertical blanking interval etc. is performed.
Summarizing the problems to be solved by the invention, as explained above, the circuit in FIG. 8 separates data by the comparator 16 from an intermediate voltage value obtained by dividing the outputs of the top peak detection circuit 11 and the bottom peak detection circuit 12 for detecting a top peak and a bottom peak of an input VBI signal by the resistors R11 and R12 using an output pulse (control signal) of the CRI window circuit 15 and using as a reference voltage (slice level) a voltage sampled and held by the sampling/holding circuit 13 in the CRI signal interval.
Accordingly, the circuit in FIG. 8 is suitable for separating data from a VBI signal having a CRI signal, but cannot generate the slice level well for a VBI signal having only a reference signal and cannot separate a reference signal well by the comparator 16.
Also, the circuit in FIG. 9 detects the pedestal level Vp of the input VBI signal in the sampling/holding circuit 25, sets the relative slice levels Vs1 and Vs2 based on a sync chip level Vc and the pedestal level Vp, and performs synchronizing separation and data slicing in the comparators 27 and 28 by using the slice levels Vs1 and Vs2.
Accordingly, since the circuit in FIG. 9 generates a slice level regardless of the data portion of the VBI signal, it is suitable for separating data of a VBI signal having only a reference signal but is not optimal for separating from a VBI signal having a CRI signal.